FIG. 1 illustrates an example of an integrated circuit chip assembly. Two chips 1 and 2, respectively to the left and to the right of the drawing, are assembled on a chip 3 and are separated therefrom by a silicon interposer plate 4.
Chip 1, as well as chip 2, comprises a silicon substrate 5 coated with a silicon oxide layer 6, itself coated with a silicon layer 7. Silicon layer 7, currently designated as SOI (Silicon on Insulator), is coated with an interconnection structure 8 comprising several metallization levels 9 separated by insulating layers.
Chip 3 comprises a silicon substrate 10 coated with a silicon oxide layer 11, itself coated with an SOI layer 12. SOI layer 12 is coated with an interconnection structure 13 comprising several metallization levels 14 separated by insulating layers.
Interconnection structures 8 of chips 1 and 2 are arranged opposite to interconnection structures 13 of chip 3.
In SOI layers 7 are formed electronic components, not shown, for example, logic components. Some of these electronic components are interconnected via external pads 17 of interconnection structures 8, connected to ends of vias 18, vias 18 being connected to external pads 19 of interconnection structure 13 and crossing interposer plate 4.
Optoelectronic components, not shown, are formed in SOI layer 12 of chip 3.
FIGS. 2A and 2B are respectively a top view and a cross-section view along plane BB of a portion of an optical waveguide formed in SOI layer 12 of chip 3 of FIG. 1. Lightly-doped P-type SOI layer 12 (P−) comprises a portion entirely surrounded with silicon oxide, which forms core 20 of the optical waveguide. Core 20 resting on oxide layer 11 is laterally delimited by two wafers 21 filled with oxide crossing SOI layer 12 and is covered with an upper oxide layer. In the shown example, the upper oxide layer comprises a central portion 23 surrounded with two lateral portions 24 deeper than central portion 23. Central portion 23, which is shallower, for example results from a thermal oxidation, and lateral portions 24 for example correspond to trenches filled with oxide which do not cross SOI layer 12.
For switching speed and bulk reasons, the electronic components of chips 1 and 2 are formed in very thin SOI layers 7 having thicknesses for example in the range from 5 to 10 nm.
It is desired to protect some at least of the electronic components of chips 1 and 2 against overvoltages, for example, during an electrostatic discharge capable of occurring while chips 1 and 2 comprising the components to be protected are still unconnected. Generally, a protection component connected across the component to be protected is used. Such a protection component may for example be an avalanche diode, a bipolar transistor, or a unidirectional or bidirectional Shockley diode.
It would be desirable to include the protection components in SOI layer 7 where the component to be protected is formed. However, given the small thickness of SOI layer 7, a protection component formed in this layer would be damaged or destroyed by the currents capable of flowing on occurrence of an overvoltage.
Thereby, electronic integrated circuit components formed in very thin SOI layers result in having to be protected by discrete external protection components. Such discrete external protection components are, for example, mounted on a printed circuit having the integrated circuit containing the component to be protected mounted thereon.
The need to use discrete external protection components results in bulk and assembly cost issues.
A device of protection against overvoltages of elements formed in a thin SOI layer is thus needed.